MIT researchers have developed a brand new fabrication method that would enable the production of more energy efficient electronics by stacking multiple functional components on top of 1 existing circuit.
In traditional circuits, logic devices that perform computation, like transistors, and memory devices that store data are built as separate components, forcing data to travel backwards and forwards between them, which wastes energy.
This recent electronics integration platform allows scientists to fabricate transistors and memory devices in a single compact stack on a semiconductor chip. This eliminates much of that wasted energy while boosting the speed of computation.
Key to this advance is a newly developed material with unique properties and a more precise fabrication approach that reduces the variety of defects in the fabric. This permits the researchers to make extremely tiny transistors with built-in memory that may perform faster than state-of-the-art devices while consuming less electricity than similar transistors.
By improving the energy efficiency of electronic devices, this recent approach could help reduce the burgeoning electricity consumption of computation, especially for demanding applications like generative AI, deep learning, and computer vision tasks.
“We have now to reduce the quantity of energy we use for AI and other data-centric computation in the long run since it is just not sustainable. We’ll need recent technology like this integration platform to proceed that progress,” says Yanjie Shao, an MIT postdoc and lead creator of two papers on these recent transistors.
The brand new technique is described in two papers (one invited) that were presented on the IEEE International Electron Devices Meeting. Shao is joined on the papers by senior authors Jesús del Alamo, the Donner Professor of Engineering within the MIT Department of Electrical Engineering and Computer Science (EECS); Dimitri Antoniadis, the Ray and Maria Stata Professor of Electrical Engineering and Computer Science at MIT; in addition to others at MIT, the University of Waterloo, and Samsung Electronics.
Flipping the issue
Standard CMOS (complementary metal-oxide semiconductor) chips traditionally have a front end, where the lively components like transistors and capacitors are fabricated, and a back end that features wires called interconnects and other metal bonds that connect components of the chip.
But some energy is lost when data travel between these bonds, and slight misalignments can hamper performance. Stacking lively components would cut back the space data must travel and improve a chip’s energy efficiency.
Typically, it’s difficult to stack silicon transistors on a CMOS chip since the extreme temperature required to fabricate additional devices on the front end would destroy the present transistors underneath.
The MIT researchers turned this problem on its head, developing an integration technique to stack lively components on the back end of the chip as an alternative.
“If we will use this back-end platform to place in additional lively layers of transistors, not only interconnects, that might make the mixing density of the chip much higher and improve its energy efficiency,” Shao explains.
The researchers completed this using a brand new material, amorphous indium oxide, because the lively channel layer of their back-end transistor. The lively channel layer is where the transistor’s essential functions happen.
On account of the unique properties of indium oxide, they will “grow” an especially thin layer of this material at a temperature of only about 150 degrees Celsius on the back end of an existing circuit without damaging the device on the front end.
Perfecting the method
They fastidiously optimized the fabrication process, which minimizes the variety of defects in a layer of indium oxide material that is simply about 2 nanometers thick.
A number of defects, referred to as oxygen vacancies, are needed for the transistor to change on, but with too many defects it won’t work properly. This optimized fabrication process allows the researchers to provide an especially tiny transistor that operates rapidly and cleanly, eliminating much of the extra energy required to change a transistor between on and off.
Constructing on this approach, in addition they fabricated back-end transistors with integrated memory which are only about 20 nanometers in size. To do that, they added a layer of fabric called ferroelectric hafnium-zirconium-oxide because the memory component.
These compact memory transistors demonstrated switching speeds of only 10 nanoseconds, hitting the limit of the team’s measurement instruments. This switching also requires much lower voltage than similar devices, reducing electricity consumption.
And since the memory transistors are so tiny, the researchers can use them as a platform to check the basic physics of individual units of ferroelectric hafnium-zirconium-oxide.
“If we will higher understand the physics, we will use this material for a lot of recent applications. The energy it uses may be very minimal, and it gives us quite a lot of flexibility in how we will design devices. It really could open up many recent avenues for the long run,” Shao says.
The researchers also worked with a team on the University of Waterloo to develop a model of the performance of the back-end transistors, which is a crucial step before the devices might be integrated into larger circuits and electronic systems.
In the long run, they wish to construct upon these demonstrations by integrating back-end memory transistors onto a single circuit. In addition they want to boost the performance of the transistors and study methods to more finely control the properties of ferroelectric hafnium-zirconium-oxide.
“Now, we will construct a platform of versatile electronics on the back end of a chip that enable us to attain high energy efficiency and many various functionalities in very small devices. We have now an excellent device architecture and material to work with, but we’d like to maintain innovating to uncover the final word performance limits,” Shao says.
This work is supported, partially, by Semiconductor Research Corporation (SRC) and Intel. Fabrication was carried out on the MIT Microsystems Technology Laboratories and MIT.nano facilities.