{"id":371057,"date":"2026-07-24T04:10:23","date_gmt":"2026-07-23T22:40:23","guid":{"rendered":"https:\/\/ebiztoday.news\/?p=371057"},"modified":"2026-07-24T04:10:23","modified_gmt":"2026-07-23T22:40:23","slug":"amd-raises-the-ai-stakes-with-helios-venice-and-robotics-computerworld","status":"publish","type":"post","link":"https:\/\/ebiztoday.news\/index.php\/2026\/07\/24\/amd-raises-the-ai-stakes-with-helios-venice-and-robotics-computerworld\/","title":{"rendered":"AMD raises the AI stakes with Helios, Venice and robotics \u2013 Computerworld"},"content":{"rendered":"
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Venice scales to 256 Zen 6 cores with support for 512 threads, 16 memory channels, as much as 1GB of L3 cache per socket, together with PCIe 6.0 and CXL 3.1 connectivity. AMD can also be offering several Venice configurations for other applications, including general-purpose servers, high-frequency workloads, GPU hosts and high-density CPU sandbox systems used to execute agent tools.<\/p>\n

Treating the CPU solely as a GPU host understates its role. Gateways, tokenization, vector search, databases and short-lived code execution stress different mixes of per-core performance, thread count, memory bandwidth and I\/O. Specifically, AMD\u2019s internal testing shows Venice significantly outperforming its current EPYC 9965 Turin CPU across five parts of the agentic AI pipeline, including gateway processing, context assembly, vector search, enterprise applications and short-lived tool execution. Individual gains vary by workload, but AMD details the general generational improvement at as much as a 1.7 times lift. As with the MI455X figures though, these comparisons come from AMD and would require independent validation.<\/p>\n

Pensando networking and ROCm software advance<\/h2>\n

Keeping GPUs fed with data and coordinating traffic across racks directly affects utilization and operating costs. In reality, GPU utilization is a fairly sad state of affairs currently for a few of the most important frontier model providers.<\/p>\n<\/div>\n

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Venice scales to 256 Zen 6 cores with support for 512 threads, 16 memory channels, as much as 1GB of L3 cache per socket, together with PCIe 6.0 and CXL 3.1 connectivity. AMD can also be offering several Venice configurations for other applications, including general-purpose servers, high-frequency workloads, GPU hosts and high-density CPU sandbox systems […]<\/p>\n","protected":false},"author":1,"featured_media":371058,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[10],"tags":[2711,17165,54183,3513,4540,16785,16423],"class_list":["post-371057","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technology","tag-amd","tag-computerworld","tag-helios","tag-raises","tag-robotics","tag-stakes","tag-venice"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t