BoolSi raises $6M to compile unusual code into custom chips

Chip-design startup BoolSi Inc. today announced it has raised $6 million in seed funding to construct a compiler that turns unusual software into custom hardware, removing the years of digital-logic training that chip design has all the time demanded.

Co-founder and Chief Executive Mihailo Isakov built BoolSi to aim at FPGAs, the field-programmable gate arrays that will be reconfigured after manufacturing and dropped in next to a central processing unit. The workflow is easy on the user’s end. A developer points the compiler at a slow spot in a program written in C, C++ or one other high-level language and BoolSi returns a custom circuit and a driver.

The corporate says that takes minutes. Doing the identical work by hand takes months.

Custom hardware can run fixed workloads far faster than a general-purpose processor. It spreads the computation across dedicated gates and wires that each one run directly, which avoids the fetch-decode-execute overhead a CPU pays on every instruction. The tradeoff has all the time been difficulty.

Designing chips is closer to watchmaking than to programming, with thousands and thousands of subcircuits that should coordinate precisely. Open-source resources are thin and the associated fee of entry runs into years. Most software engineers never get a path into hardware, even when their applications would profit from it.

BoolSi reframes the issue as learning what a program does, not translating the way it is written. The corporate trains machine-learning models that converge into fully digital circuits, using the source program itself as an artificial data generator. A fuzzer explores the input space and turns every run into an exactly labeled training example, which the corporate says makes 100% accuracy each achievable and required. For verification, BoolSi trains several independent models in parallel and formally checks them against each other.

The corporate makes the case with one benchmark, a regex routine that scans text for email addresses. Compiled with gcc -O3, the routine took 2.66 milliseconds on an ARM Cortex-A9 processor. A single BoolSi hardware agent did it in 0.325 milliseconds. That’s about eight times faster. Eight agents running together finished in 0.042 milliseconds, 63 times quicker than the CPU.

BoolSi pitches the work against existing high-level synthesis tools comparable to Vivado HLS, Catapult and Bambu. It argues those tools made hardware engineers more productive but never opened the sphere to software developers.

The startup is aiming first at embedded developers in robotics, where jobs comparable to motor-control loops, sensor fusion and model-predictive control hammer general-purpose processors again and again. A personal beta is ready to open within the third quarter. BoolSi is starting with FPGAs because they let developers ship straight away, and it expects the underlying toolchain to increase to custom ASIC chips as workloads settle.

The seed round was led by Advantageous Structure Ventures, an F-Prime fund, with Pillar VC, Fifth Quarter Ventures and Coalition Ventures participating.

Photo: BoolSi